5. Power to DRAM is sent by motherboard and the RAM manages it through
6. How many bank groups is a 2GB DRAM die split into?
7. A 2GB DRAM Die has how many total banks
8. Inside the bank is a massive ____ with 65,536 cells tall by 8,192 cells wide.
9. In order to access 17 billion memory cells, we need to use
10. In 31 bit address, the first 3 bits are for
11. In 31 bit address, 2 bits are for
12. In 31 bit address, 16 bits are for
13. Because memory chip writes 8 bits at a time,
14. In 31 bit address, 10 bits are for
15. 31 bit address is broken into
16. 31 bit address data is sent using ____ wires
17. A memory cell inside of an array is called
18. Part 1 of DRAM cell is a capacitor that
19. Part 2 of DRAM cell is a transistor that
20. The DRAM capacitor is shaped like
21. The word line wire connects to the ____ of the transistor
22. The bit-line wire connects to
23. Applying a voltage to the wordline
24. In an array, each of the word lines is connected in
25. Bitlines are connected in
26. 15 bits are sent to a Row Decoder to
27. What gets turned on when a row is active
28. 10 bits go into Column multiplexer and
29. Where are the Sense Amplifiers
30. The first 5 bits in Read process do not select specific bank
31. Wordlines in a bank are turned off
32. 16 bit Row Adress
33. If an individual capacitor holds a 1, and is charged to 1 volt
34. What detects change of voltage on bitline
35. The sense amplifier does what to voltage of .5V+ on the bitline?
36. If a 0V is stored in a capacitor,
37. 10 Bit column address is used by Column Multiplexer to connect the corresponding bitlines to the Read Driver, which sends 8 Voltages over the IO Data wires to the CPU
38. Writing Data is completely different from reading
39. In writing process, 8 bits to be written are sent to the chip
40. In writing and reading, bank gets selected and capacitors become isolated, and bitlines are precharged to .5V
41. Sense Amplifiers change voltage to 1 or 0 Volts, thus “opening” up the row.
42. The multiplexer connects 8 bitlines to Write Driver, which
43. Write Drivers are stronger than Sense Amplifier
44. Writing and Reading DO NOT happen concurrently with all 4 chips in the shared memory channel
45. Newer DDR versions have a smaller Charge for binary 1 and also a smaller Precharge voltage number
46. What’s the amount of time it takes to refresh 65,546 rows
47. DRAM requests per second
48. Open Row process
49. With Row Hit/Page hit
50. 128 bit wires connect into Burst Buffers
51. Inside the Sense Amplifier, you will find a Cross-Coupled Inverter